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Extreme-Scale, Nano & Fundamental Engineering

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Nanoelectronics Engineer

Electronics at the scale where interfaces and contacts dominate the electrical behaviour.

Mid Full-Time On-site — Kolkata, West Bengal, India Permanent

Compensation

Engagement

Full-Time

Permanent role. Full-time commitment. This is an on-site role at Kolkata. It is not remote and not hybrid.

Scope of role

Drive specific initiatives with minimal supervision. Deepen craft. Begin mentoring others.

Research classification

Applied engineering Established science Level 3 · Engineer and Scientist Semiconductors, Electronics & Micro/Nano Systems →

Engineering to a specification, on established science, for something that has to work. Designs, analyses against requirements, test evidence, and maintainable engineering artefacts.

Established science. Rests on settled physics and engineering. The work applies it; it is not what is under test here.

Scale range 10^-9 m to 10^-6 m

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10-100 m 100 m 10100 m
Experiments reach here 3 bands no experiment reaches This role

Silicon is the most established engineering material there is, and a simulated device is still not a fabricated one. This division separates, in every report, what was simulated in TCAD or SPICE, what was measured on a fabricated part, and what a partner foundry has confirmed it can produce at yield. Scientific integrity is a condition of every role in this department. Assumptions are stated separately from conclusions. Uncertainty is reported. Negative and inconclusive results are written up, not discarded. Speculative work is labelled speculative, including when that makes it less impressive. Fabrication, falsification, and presenting a simulation as a measurement end an engagement here.

Scale bands are a research classification, not a claim of experimental reach. Most of this span cannot be probed by any apparatus that exists: nothing below about 10^-19 m has been measured directly, and anything at 10^26 m or beyond is inferred from observation rather than engineered. Every opportunity states the kind of work it actually is.

01 — The role

Why this role exists at EduRankAI

Department of Extreme-Scale, Nano & Fundamental Engineering, Division D07: Semiconductors, Electronics & Micro/Nano Systems. This division designs devices, models electronic systems, develops sensors, analyses device performance, and supports prototype development with partner fabrication facilities. It is an engineering division: its work is judged against a specification. This position: Electronics at the scale where interfaces and contacts dominate the electrical behaviour. Scale range for this work: 10^-9 m to 10^-6 m. Research classification: Applied engineering. Engineering to a specification, on established science, for something that has to work. Evidential standing: Established science. Rests on settled physics and engineering. The work applies it; it is not what is under test here. Silicon is the most established engineering material there is, and a simulated device is still not a fabricated one. This division separates, in every report, what was simulated in TCAD or SPICE, what was measured on a fabricated part, and what a partner foundry has confirmed it can produce at yield. Scale bands are a research classification, not a claim of experimental reach. Most of this span cannot be probed by any apparatus that exists: nothing below about 10^-19 m has been measured directly, and anything at 10^26 m or beyond is inferred from observation rather than engineered. Every opportunity states the kind of work it actually is. Level 3 (Engineer and Scientist). A whole problem end to end: framing it, doing the work, and reporting the result with its limits.

02 — The work

What you will own

  • 01 Design devices against a written specification with margins stated.
  • 02 Model electronic and electromechanical systems, including the parasitics that decide whether they work.
  • 03 Develop sensors and derive their limit of detection rather than asserting it.
  • 04 Analyse device performance against specification and report where it falls short.
  • 05 Support prototype fabrication with partner facilities and record what the process actually did.
  • 06 Maintain design files and change records so a revision can be traced.
  • 07 Own a whole problem end to end: framing it, doing the work, and reporting the result with its limits.
  • 08 Review a colleague's work when asked, and say plainly when a result is not supported by its method.

03 — The expertise

What we look for

Can derive or explain the current-voltage characteristic of a diode or a MOSFET from device physics.Has simulated a circuit in SPICE and compared the result against a hand calculation.Semiconductor physics: carriers, doping, band structure, junctions.Can read a datasheet and identify the conditions a specification was measured under.Documents a design against a written specification rather than against intent.PythonC++Verilog or VHDLMATLAB or an equivalent

04 — The bar

Who thrives here

  • Education: Master's degree or doctorate in a relevant discipline, or equivalent demonstrated research output.
  • Experience: 2 to 5 years of relevant work, or a doctorate in the field.
  • Scope of the role: A whole problem end to end: framing it, doing the work, and reporting the result with its limits.
  • Must have: Can derive or explain the current-voltage characteristic of a diode or a MOSFET from device physics. Also: Has simulated a circuit in SPICE and compared the result against a hand calculation.
  • Portfolio: at least one piece of work — code, a written result, a thesis chapter, a preprint — that somebody outside your institution can read and assess. It does not need to be published.

Terms of Engagement

How working time works at this level

A scheduled week: five days, eight hours a day, with two full rest days and latitude over when within the day you work.

Type

Mid-level

Working days

5 per week

Rest days

2 per week

Scheduled week

40 hrs

Per day

8h

Measured by

Objectives agreed at the start of each cycle. Hours recorded for compliance are never used as a performance score.

Where this stands legally

Within the 9-hour day and 48-hour week ceiling of the applicable state Shops and Establishments Act, with at least 24 consecutive hours of weekly rest and a break of at least 30 minutes after five hours of continuous work. Hours are recorded for statutory compliance only. Work beyond the scheduled week is agreed in advance and compensated with time off in lieu.

The full per-level model is published at Working Hours by Level.

05 — Hiring process

What to expect after you apply

  1. 01

    Application review

    Every application is read personally within five business days. We respond either way.

  2. 02

    Take-home or live exercise

    Role-specific. Time-boxed. Real problems we are actually working on, not invented puzzles.

  3. 03

    Conversations

    Deep technical and values conversations with the team you would join. No trick questions. No panel ambushes.

  4. 04

    Offer or honest no

    If yes: digital offer letter, signed in-portal, transparent terms. If no: written feedback if you want it.

The standard

What you deliver, and how it is judged

Deliverables

  • Designs with a written specification, margins, and the simulation evidence behind them.
  • Test reports comparing measured behaviour with simulated behaviour.
  • Process notes from partner fabrication, including deviations.
  • A maturity statement per design: simulated, prototyped, or confirmed at yield.

Evaluation criteria

  • Whether the design meets its written specification with margin.
  • Whether simulation was validated against measurement where a part exists.
  • Traceability of design revisions.
  • Precision about simulated versus fabricated in every claim.

Preferred, not required

Nothing in this list is a bar to applying.

Digital or analog design experience beyond coursework.Familiarity with a microfabrication process flow and its constraints.Signal processing sufficient to characterise a sensor's noise.Version-controlled design files and a change record.RTL and a simulation or synthesis flow.MEMS design or characterisation experience.Photonic integrated circuit design.Cleanroom or test-laboratory experience.

Tools you would work in

SPICETCAD device simulationFEM multiphysics for MEMSRTL simulation and synthesis toolingPCB design toolsLaboratory instrumentation and automationGit

Reports to: Semiconductors, Electronics & Micro/Nano Systems Lead

Works with: D03, D05, D06, D08, D10, D12

Before you start

What we will collect. What it costs. What we will not do with it.

We will collect

  • Name, email, phone — Account + application updates. No marketing.
  • Resume / portfolio link — Human review of your work.
  • Date + place of birth — Identity verification only.
  • Your written responses — Selection rubric. Read by humans.
  • Government ID (later) — Anti-fraud at offer / interview stage. Not at signup.

We will never

  • Sell your data
  • Share with third-party recruiters
  • Use for advertising
  • Train models on it
  • Send marketing email

Our situation

EduRankAI is a small, independent organization building long-term capabilities in educational intelligence, advanced AI systems, and research infrastructure. We take no advertiser money, no donations with strings attached, and no investor pressure on hiring decisions. Applying is free, and every application is read by a human — recruitment, technical, academic and leadership teams. It buys us the right to be honest.

Full transparency policy Questions? Email us

Ready to apply?

We read every application personally. If you are the right person for this role — regardless of pedigree, background, or where you are based — you will hear back from us within five business days.

Apply through this page. You will be asked for your education, your experience, and links to work we can actually read — a repository, a write-up, a thesis chapter, a preprint. Send the piece of work you would defend, not the one with the best title. If a result in it turned out to be wrong, say so; we would rather read that than not know. Every application is read by a person. We assess applications on evidence of the work. We do not filter on institution, on age, on gender, on caste, on religion, on disability, or on where you are from. If any part of this process is inaccessible to you, tell us and we will change it for you.

Mid Full-Time

Nanoelectronics Engineer

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