Eight scaffolded experiments in the Virtual Labs format. Each experiment carries its own Aim, Theory, Procedure, a genuinely-computing Simulation, a checkable Self-Assessment and References. Pick an experiment on the left; every simulator runs live in your browser with no server round-trips.
Aim
Theory
Procedure
Netlist Builder
Sources
Combinational gates
Sequential
Presets
Nets
CLK SPEED tick 0 · probed nets scroll right
CMOS Transistor View
GateA0B0
Live Inputs
No INPUT/CLOCK sources yet.
Truth Table
Add INPUTs and PROBE outputs, then generate.
Circuit Stats
Combinational nets re-evaluate each tick until the network settles (max 50 iterations, so feedback latches converge). Flip-flops capture on the clock rising edge only.
Function Definition
Variables
Click a truth-table output cell to cycle 0 → 1 → X (don't-care). Minimization updates live.
Karnaugh Map & Minimal SOP
F = 0
Block
Live Inputs
Output
Truth Table
Drive the Flip-Flops
All three share one clock. Set the data inputs, then pulse the clock to clock in new state on the rising edge. Behaviour is computed from each device's characteristic equation.
Stored State (Q)
Excitation / Characteristic Tables
Machine
Current State
Step the Machine
Input Trace
State Transition Diagram
State Transition Table
Clock & Flip-Flop
1.40
0.12
0.08
0.04
Gate Delays (path FF1 - U1 - U2 - U3 - FF2)
0.20
0.30
0.18
0.04
All times in nanoseconds. The combinational path has three logic stages; each net carries one wire delay. Arrival times flow forward from FF1.Q; required times flow backward from FF2.D.
Setup & Hold Checks
Per-Node Arrival / Required / Slack
Device & Sizing
Gate
2.0
20
1.20
2.0
PMOS is sized at (mu_n/mu_p) times the NMOS to equalise rise and fall drive. Delay model: tp = 0.69 * R_on * (C_self + C_load), Elmore style. FO4 = an inverter driving four identical copies of itself.
Computed Delays
Propagation delay tp vs fanout (electrical effort)
Operating Point
0.15
1.00
1.00
50
0.35
f in GHz, C in pF, V in volts so powers come out in milliwatts. Dynamic = a*C*Vdd^2*f. Short-circuit scales with (Vdd - 2Vt). Leakage = Ioff*Vdd with Ioff exp(-Vt/nVth) subthreshold dependence.
Power Breakdown
Bars: dynamic / short-circuit / leakage. Curve overlay: total power vs Vdd (quadratic).